Improving Direct-mapped Cache Performance By The Addition Of A

    Associative property performance task. Half or more of their performance in the memory hierar- chy if the (i.e., lack of associativity) are presented in s ection 3. an the target procedure may ma.

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Improving Direct-Mapped Cache Performance by the Addition
of a Small Fully-Associative Cache and Prefetch Buffers
Norman P. Jouppi
Digital Equipment Corporation Western Research Lab
100 Hamilton Ave., Palo Alto, CA 94301
Projections of computer technology forecast proces-
sors with peak performance of 1,000 MIPS in the rela-
tively near future. These processors could easily lose
half or more of their performance in the memory hierar-
chy if the hierarchy design is based on conventional
caching techniques. This paper presents hardware tech-
niques to improve the performance of caches.
Miss caching
places a small fully-associative cache
between a cache and its refill uath. Misses in the cache
that hit in the miss cache ha;e only a one cycle miss
penalty, as o
posed to a many cycle miss penalty without
the mns cat e.
Small miss caches of 2 to 5 entries are
shown to be very effective in removing mapping conflict
misses in first-level direct-mapped caches.
is an improvement to miss caching
-associative cache with the vic-
tim of a miss and not t
e requested line. Small victim
caches of 1 to 5 entries are even more effective at remov-
ing conflict misses than miss caching.
Stream buffers
refetch cache lines statting at a
cache miss address.
fh e prefetched data is placed in the
buffer and not in the cache.
Stream buffers are useful in
removing capacity and compulsory cache misses, as well
as some instruction cache conflict misses. Stream buf-
fers are more effective than previously investigated
next slower level in the
An extension to
prefetching along multiple intertwined data reference
Together, victim caches and stream buffers reduce
the miss rate of the first level in the cache hierarchy by a
factor of two to three on a set of six large benchmarks.
1. Introduction
Cache performance is becoming increasingly impor-
tant since it has a dramatic effect on the performance of
advanced processors. Table l-l lists some cache miss
times and the effect of a miss on machine performance.
Over the last decade, cycle time has been decreasing
much faster than main memory access time. The average
number of machine cycles per instruction has also been
decreasing dramatically, especially when the transition
from CISC machines to RISC machines is included.
These two effects are multiplicative and result in tremen-
dous increases in miss cost. For example, a cache miss
on a VAX 1 l/780 only costs 60% of the average instruc-
tion execution. Thus even if every instruction had a
cache miss, the machine performance would slow down
by only 60%! However, if a RISC machine like the
WRL Titan [lo] has a miss, the cost is almost ten in-
struction times. Moreover, these trends seem to be con-
tinuing, especially the increasing ratio of memory access
time to machine cycle time. In the future a cache miss
all the way to main memory on a superscalar machine
executing two instructions per cycle could cost well over
100 instruction times! Even with careful application of
well-known cache design techniques, machines with
main memory latencies of over 100 instruction times can
easily lose over half of their potential performance to the
memory hierarchy. This makes both hardware and
software research on advanced memory hierarchies in-
creasingly important.
cycles cycle mem miaa
time time
(na) (cycles) (in&r)
10.0 200
1200 6
WRL Titan 1.4 45 540 12
280 70
The increasing cost of cache misses
This paper investigates new hardware techniques for
increasing the performance of the memory hierarchy,
Section 2 describes a baseline design using conventional
caching techniques. The large performance loss due to
the memory hierarchy is a detailed motivation for the
techniques discussed in the remainder of the paper.
Techniques for reducing misses due to map
ing conflicts
(i.e., lack of associativity) are presented in s
ection 3. An
extension to prefetch techniques called stream buffering
is evaluated in Section 4. Section 5 summarizes this
work and evaluates promising directions for future work
2. Baseline Design
Figure 2-l shows the range of configurations of in-
terest in this study. The CPU, floating-point unit,
memory management unit (e.g., TLB), and first level in-
struction and data caches are on the same chip or on a
single high-speed module built with an advanced paek-
aging technology.
(We will refer to the central processor
as a single chip in the remainder of the paper, but chip or
CH2887-8/90/0000/0384$01.00 (D1990lEEE
module is implied.) The cycle time off this chip is 3 to 8
times longer than the instruction issue rate (i.e., 3 to 8
instructions can issue m one off-chip clock cycle). This
is obtained either by having a very fast on-chip clock
(e.g., superpipeiining [S]), by issuing many instructions
per cycle (e.g., superscalar or VLIW), and/or by using
higher speed technologies for the processor chip than for
the rest of the system (e.g., GaAs vs. BiCMOS).
The expected size of the on-chip caches varies with
the implementation technology for the processor, but
higher-speed technologies generally result in smaller on-
chip caches. For example, quite large on-chip caches
should be feasible in CMOS but only small caches are
feasible in the near term for GaAs or bipolar processors.
Thus, although GaAs and bipolar are faster, the higher
miss rate from their smaller caches tends to decrease the
actual system performance ratio between GaAs or
bipolar machines and dense CMOS machines to less than
the ratio between their gate speeds. In all cases the first-
level caches are assumed to be direct-mapped, since this
results in the fastest effective access time [7]. Line sizes
in the on-chip caches are most likely in the range of I6B
to 32B. The data cache may be either write-through or
write-back, but this paper does not examine those
Instrucmn I*s”o r*te:
%z: lime
Fiyre 2-1: Baseline design
The second-level cache is assumed to range from
512XB to 16M3. and to be built from very high speed
static RAMS. it is assumed to be direct-mapped for the
same reasons as the first-level caches. For caches of this
size access times of 16 to 30ns are likely. This yields an
access time for the cache of 4 to 30 instruction times.
The relative speed of the processor as compared to the
access time of the cache Implies that the second-level
cache must be ipelmed in order for it to provide suf-
ficient bandwid % .
For example, consider the case where
the first-level cache is a write-through cache. Since
stores typically occur at an average rate of 1 in every 6 or
7 instructions, an unpipelined external cache would not
have even enough bandwidth to handle the store traffic
for access
greater than
instruction times.
Caches have been pipelined in mainframes for a number
of years [12], but this is a recent development for
workstations. Recently cache chips with ECL I/O’s and
registers or latches on their inputs and outputs have ap-
peared; rhese are ideal for pipelined caches. The number
of pipeline stages in a second-level cache access could be
2 or 3 depending on whether the pipestage going from
the processor chip to the cache chips and the pipestage
returning from the cache chips to the processor are full or
half pipestages.
In order to provide sufficient memory for a proces-
sor of this speed (e.g., several megabytes per MIP), main
memory should be in the range of 512MB to 4GB. This
means that even if 16Mb DRAMS are used that it will
contain roughly a thousand DRAMS. The main memory
system probably will take about ten times longer for an
access than the second-level cache. This access time is
easily dominated by the time required to fan out address
and data signals among a thousand DRAMS spread over
many cards.
Thus even with the advent of faster
DRAMS, the access time for main memory may stay
roughly the same. The relatively large access time for
main memory in turn requires that second-level cache
line sizes of 128 or 256B are needed. As a counter
example, consider the case where only 16B are returned
after 320ns. This is a bus bandwidth of SOMB/sec.
Since a IO MIP processor with this bus bandwidth would
be bus-bandwidth limited in copying from one memory
location to another [l 11, little extra erformance would
be obtained by the use of a 100 to 1, loo MlP processor.
This is an important consideration in the system perfor-
mance of a processor.
Several observations are in order on the baseline
system. First, the memory hierarchy of the system is
actually quite similar to that of a machine like the VAX
1 l/780 [3,4], only each level in the hierarchy has moved
one step closer to the CPU. For example, the 8KB
board-level cache in the 780 has moved on-chip. The
512KB to 16MB main memory on early VAX models
has become the board-level cache. Just as in the 780’s
main memory, the incoming transfer size is large
(128-256B here vs. 512B pages in the VAX). The main
memory in this system is of similar size lo the disk sub-
systems of the early 780’s and performs similar functions
such as paging and file system caching.
The actual parameters assumed for our
baseline sys-
tem are 1,000 MIPS peak instruction issue rate, separate
4KB first-level instruction and data caches with 16B
Iines, and a IMB second-level cache with I28B lines.
The miss penalties are assumed to be 24 instruction times
for the first level and 320 instrucrion times for the
level. The characteristics of the test programs
used in
this study are given in Table 2-l. These benchmarks are
reasonably long in comparison with most traces in use
today, however the effects of multiprocessing have not
been modeled in this work The first-level cache miss
rates of these programs running on the baseline system
configuration are given in Table 2-2.
program dynamic data tot81 program
in&r. rmf8.
C co*ilar
193.411 PC
board CAD
Unix utility
50.3M 149.71
bo8rd CAD
Unpack 144.8H
40.7~ 185.5&l 100x100 nwamric
7.4M 31.OM Lm (n-rid
484.51 186.3H 672.81
Table 2-1: Test program characteristics
The effects of these miss rates are given graphically
in Figure 2-2. The region below the solid line gives the
net performance of the system, while the region above
the solid line gives the performance lost in the memory
hierarchy. For example, the difference between the top
dotted line and the bottom dotted line gives the petfor-
mance lost due to first-level data cache misses. As can
be seen in Figure 2-2, most benchmarks lose over half of
their potential performance in first level cache misses.
Only relatively small amounts of performance are lost to
second-level cache misses. This is primarily due to the
large second-level cache size in comparison to the size of
the programs executed.
Longer traces [2] of larger
programs exhibit significant numbers of second-level
cache misses. Since the test suite used in this paper is
too small for significant second-level cache activity,
second-level cache misses will not be investigated in
detail, but will be left to future work.
baseline miss rate
in&r. data
.---------------------- .-e--w-
0.096 0.120
0.061 0.062
0.017 0.039
0.000 0.144
0.000 0.273
Table 2-2: Baseline system fist-level cache miss rates
100 ccom grr
2 3 Bcnchmarli+ 5
Baseline design performance
Since the exact parameters assumed are at the ex-
treme end of the ranges described (maximum perfor-
mance processor with minimum size caches), other con-
figurations would lose proportionally less performance in
their memory hierarchy. Nevertheless, any configuration
in the range of interest will lose a substantial proportion
of its potential performance in the memory hierarchy.
This means that the greatest leverage on system perfor-
mance will be obtained by improving the memory hierar-
chy performance, and not by attempting to further in-
crease the performance of the CPU (e.g., by more ag-
gressive parallel issuing of instructions). Techniques for
improving the performance of the baseline memory
hierarchy at low cost are the subject of the remainder of
this paper. Finally, in order to avoid compromising the
performance of the CPU core (comprising of the CPU,
FPU, MMU, and first level caches), any additional
hardware required by the techniques to be investigated
should reside outside the CPU core (Le.. below the first
level caches). By doing this the additional hardware will
only be involved during cache misses, and therefore will
not be in the critical path for normal instruction execu-
3. Reducin Conflict Misses: Miss Caching and
Victim aching 8
Misses in caches can be classified into four
compulsory, capacity [7],
coherence. Conflict misses are misses that would not
occur if the cache was fully-associative and had LRU
replacement. Compulsory misses are misses required in
any cache organization because the
references to an instruction or piece 0
are the first
misses occur when the cache size is not sufficient to hold
data between references. Coherence misses are misses
that occur as a result of invalidation to preserve mul-
tiprocessor cache consistency.
Even though direct-mapped caches have more con-
flict misses due to their lack of associativity, their perfor-
mance is still better than set-associative caches when the
access time costs for hits are considered. In fact, the
direct-mapped cache is the only cache configuration
where the critical path is merely the time
access a RAM [9]. Conflict misses typically account
between 20% and 40% of all direct-mapped cache
misses [7]. Figure 3-1 details the percentage of misses
due to conflicts for our test suite. On average 39% of the
first-level data cache misses are due to conflicts, and
29% of the first-level instruction cache misses are due
Since these are significant percentages, it
would be nice to “have our cake and eat it too” by some-
how providing additional associativity without adding to
the critical access path for a direct-mapped cache.
Figure 3-1:
Conflict misses, 4KB I and D, 16B lines
3.1. Miss Caching
We can add associativity to a direct-mapped cache
by placing a small
cache on-chip between a first-
level cache and the access port to the second-level cache
(Figure 3-2). A miss cache is a small fully-associative
cache containing on the order of two to five cache lines
of data. When a miss occurs, data is returned not only to
the direct-mapped cache, but aiso to the miss cache un-
der it, where it replaces the least recently used item.
Each time the upper cache is probed, the miss cache is
probed as well. If a miss occurs in the up er cache but
the address hits in the miss cache, then the
cache can be reloaded in the next cycle from the miss
cache. This replaces a long off-chip miss penalty with a
short one-cycle on-chip miss. This arrangement satisfies
the requirement that the critical path is not worsened,
since the miss cache itself is not in the normal critical
path of processor execution.
3-2: Miss cache organization
The success of different miss cache organizations at
removing conflict misses is shown in Figure 3-3. The
fvst observation to be made is that many more data con-
flict misses are removed by the miss cache than instruc-
tion conflict misses. This can be explained as follows.
instruction confIicts tend to be widely spaced because
the instructions within one procedure will not conflict
with each other as long as the procedure size is less than
the cache size, which is almost always the case. Instruc-
tion conflict misses are most likely when another proce-
is called. The target procedure may ma
with respect to the calling procedure, Y
possib y resulting
large overlap. Assuming at least 60 different in-
stntctions are executed in each procedure, the conflict
misses would span more than the 15 lines in the max-
imum size miss cache tested. In other words, a small
miss cache could not contain the entire overlap and so
would be reloaded repeatedly before it could be
This type of reference pattern exhibits the worst miss
cache performance.
Data conflicts, on the other hand, can be quite
closely spaced. Consider the case where two character
strings are being compared. If the points of comparison
of the two strings happen to map to the same line, alter-
nating references to different strings will always miss in
the cache. In this case a miss cache of only two entries
would remove all of the conflict misses. Obviously this
is another extreme of performance and the results in
Figure 3-3 show a range of performance based on the
program involved. Nevertheless, for 4KB data caches a
miss cache of only 2 entries can remove 25% percent of
the data cache conflict misses on average,’ or 13% of the
data cache misses overall. If the miss cache is increased
to 4 entries, 36% percent of the conflict misses can be
removed, or 18% of the data cache misses overall. After
four entries the improvement from additional miss cache
entries is minor, only increasing to a 25% overall reduc-
tion in data cache misses if 15 entries are provided.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Numk of entries in miss cache
Key- - Ll I-cache
- LlDeac
3-3: Conflict misses removed by miss caching
Since doubling the data cache size results in a 32%
reduction in misses (over this set of benchmarks when
increasing data cache size from 4K to 8K), each ad-
ditional line in the fist level cache reduces the number
misses by approximately 0.13%. AIthough the miss
cache requires more area per bit of storage than lines in
the data cache, each line in a two line miss cache effects
a 50 times larger marginal improvement in the miss rate,
so this should more than cover any differences in layout
Comparing Figure 3-3
Figure 3-1, we see that
the higher the percentage of misses due to conflicts, the
more effective the miss cache is at eliminating them. For
example, in Figure 3-1
has by far the highest ratio of
confict misses to total data cache misses. Similarly, grr
and yacc also have greater than average ercentages of
conflict misses, and the miss cache helps t ese programs
significantly as well.
and ccom have the lowest
‘Throughout this paper lhc average
reduction in miss rates is used as
a metric. This is computed by calculating the percent reduction in miss
rate for each benchmark. and then taking the average of these per-
centages. This has the advantage that it is independent of the number
memory references made
by each program. Furthermore, if
programs have widely different miss rates. the average percent reduc-
tion in miss rate gives equal weighting to each benchmark. This is in
contrast with the percent reduction in average miss rate, which weights
with the highest miss rate most heavily.
percentage of conflict misses, and the miss cache
removes the lowest percentage
conflict misses from
these programs.
This results from the fact that if a
program has a large percentage of data contlict misses
then they must be clustered to some extent because of
their overall density. This does not prevent programs
with a small number of conflict misses such as
benefiting from a miss cache, but it seems that as the
percentage of conflict misses increases, the percentage of
these misses removable by a miss cache increases.
3.2. Victim Caching
Consider a system with a direct-mapped cache and a
miss cache. When a miss occurs, data is loaded into both
the miss cache and the direct-mapped cache. In a sense,
this duplication of data wastes storage space in the miss
cache. The number of duplicate items in the miss cache
can range from one (in the case where all items in the
miss cache map to the same line in the direct-mapped
cache) to all of the entries (in the case where a series of
misses occur which do not hit in the miss cache).
To make better use of the miss cache we can use a
different replacement algorithm for the small fully-
associative cache [5]. Instead of loading the requested
data into the miss cache on a miss, we can load the
fully-associative cache with the victim line from the
direct-mapped cache instead. We call this
victim caching
(see Figure 3-4). With victim caching, no data line ap-
pears both in the direct-map ed
cache and the victim
cache. This follows from the act that the victim cache is
loaded only with items thrown out from the direct-
mapped cache.
In the case of a miss in the direct-
mapped cache that hits in the victim cache, the contents
of the direct-mapped cache line and the matching victim
cache line are swapped.
Victim cache organization
Depending on the reference stream, victim caching
can either be a small or significant improvement over
miss caching. The magnitude of this benefit depends on
the amount of duplication in the miss cache. Victim
caching is always an improvement over miss caching.
As an example, consider an instruction reference
stream that calls a small procedure in its inner loop that
conflicts with the loop body.
If the total number of con-
flicting lines between the procedure and loop body were
larger than the miss cache, the miss cache would be of no
value since misses at the beginning of the loop would be
flushed out by later misses before execution returned to
the beginning of the loop. If a victim cache is used
instead, however, the number of conflicts in the loo
can be captured is doubled compared to that store
by a
miss cache. This is because one set of conflicting in-
structions lives in the direct-mapped cache, while the
other lives in the victim cache. As execution proceeds
around the loop and through the procedure call these
items trade places.
The percentage of conflict misses removed by vic-
tim caching is given in Figure 3-5. Note that victim
caches consisting of just one line are useful, in contrast
to miss caches which must have two lines to be useful.
All of the benchmarks have improved performance in
comparison to miss caches, but instruction cache perfor-
mance and the data cache performance of benchmarks
that have conflicting long sequential reference streams
improve the most.
12 3 4 5 6 7 8 9 1011
Number of entries in victim cache
Conflict misses removed by victim caching
3.3. The Effect of Direct-Mapped Cache Size on
Victim Cache Performance
Figure 3-6 shows
the performance of 1.2.4, and 15
entry victim caches when backing up direct-mapped data
caches of varying sizes.
In general smaller direct-
mapped caches benefit the most from the addition of a
victim cache. Also shown for reference is the total per-
centage of conflict misses for each cache size. There are
two factors to victim cache performance versus direct-
mapped cache size. First, as the direct-mapped cache
increases in size, the relative size of the victim cache
becomes smaller. Since the direct-mapped cache gets
larger but keeps the same line size (16B). the likelihood
of a tight mapping conflict which would be easily
removed by victim caching is reduced. Second, the
centage of conflict misses decreases slightly from KB
to 32KB. As we have seen previously, as the percentage
of conflict misses decreases, the percentage of these
misses removed by the victim cache decreases. The
effect dominates, however, since as the percentage of
conflict misses increases with very large caches (as in
[7]), the victim cache performance
Key: ---
1 entry victim crh
90 -
- -
a0 - - - - -.
pacent conflict mirses
Q LI D-cab
“1 2
4 a
cads size ito6lcEl
32 64 128
Figure 3-6:
Victim cache: vary direct-map cache size
3.4. The Effect of Line Size on Victim Cache
Figure 3-7 shows the performance of victim caches
for 4KB direct-mapped data caches of varying line sizes.
As one would expect, as the line size at this level in-
creases, the number of conflict misses also increases.
Q Ll D-cdm
16 32 64 128 256
C&m Line Size in Bytes
Figure 3-7:
Victim cache: vary data cache line size
The increasing percentage of conflict misses results
in an increasing ~mentage of these misses being
by the vtctim cache.
with victim
caches can benefit from longer line sizes more than sys-
tems without victim caches, since the victim caches help
remove misses caused by conflicts that result from
longer cache lines. Note that even if the area used for
data storage in the victim cache is held constant (i.e., the
number of entries is cut in half when the line size
doubles) the performance of the victim cache still im-
proves or at least breaks even when line sizes increase.
3.5. Victim Caches and Second-Level Caches
As the size of a cache increases, a larger percentage
of its misses are due to conflict and compulsory misses
and fewer are due to capacity misses. (Unless of course
the cache is larger than the entire program, in which case
ordy compulsory misses remain.) Thus victim caches
might be expected to be useful for second-level caches as
well. Since the number of conflict misses increases with
increasing line sizes, the large line sizes of second-level
caches wodd also tend to increase the potential useful-
ness of victim caches.
One interesting aspect of victim caches is that they
violate inclusion properties [1] in cache hierarchies.
However, the line size of the second level cache in the
baseline design is 8 to 16 times larger than the first-level
cache line sizes, so this violates inclusion as well.
Note that a first-level victim cache can contain many
lines that conflict not only at the Fit level but also at the
second level. Thus, using a first-level victim cache can
also reduce the number of conflict misses at the second
level. In investigating victim caches for second-level
caches, both configurations with and without first-level
victim caches will need to be considered.
A thorough investigation of victim caches for
megabyte second-level caches requires traces of billions
of instructions. At this time we only have victim cache
performance for our smaller test suite, and work on ob-
taining victim cache performance for multi-megabyte
second-level caches is underway.
4. Reducing Capacity and Compulsory Misses
Compulsory misses are misses required in any cache
organizatton because they are the first references to a
piece of data. Capacity misses occur when the cache size
IS not sufficient to hold data between references. One
of reducing the number of capacity and compulsory
misses is to use prefetch techniques such as longer cache
line sizes or prefetching methods [13.6]. However, line
sizes can not be made arbitrarily large without increasing
the miss rate and greatly increasing the amount of data to
be transferred. In this section we investigate techniques
to reduce capacity and compulsory misses while mitigat-
ing traditional problems with long lines and
A detailed analysis of three prefetch algorithms has
ared in 1131. P&etch always prefetches after every
re erence. Needless to sa
system since many
leve -one cache accesses
take r
this is impractical in our base
place in the time required to initiate a single level-two
cache reference. This is especially true in machines that
fetch multiple instructions per cycle from an instruction
cache and can concurrently perform a load or store per
cycle to a data cache.
Prefetch on miss
prefifch are more promising techniques. On a miss
always fetches the next line as well. It
can cut the number of misses for a purely sequential
reference stream in half.
Tagged preferch can
do even
better. In this technique each block has a tag bit as-
sociated with it. When a block is prefetched, its tag bit is
set to zero. Each time a block is used its tag bit is set to
one. When a block undergoes a zero to one transition its
successor block is prefetched. This can reduce the num-
ber of misses in a purely sequential reference stream to
zero, if fetching is fast enough. Unfortunately the large
latencies in the base system can make this impossible.
Consider Figure 4-1, which gives the amount of time (in
instruction issues) until a prefetched line is
during the execution of
risingly, since the
line size is four instructions, prefetc
ed lines must
received within four instruction-times to keep up
the machine on uncached straight-line code. Because the
base system second-level cache takes many cycles to ac-
cess, and the machine may actually issue many
tions per cycle, tagged prefetch may only have a one-
cycle-out-of-many head start on providing the required
ccom I-cache prcfctch, 16B lines
- prcfetch on miss
:\ ------ taggcdpnfach
‘$1 -- - - prefetch
2 4 6 8 10 12 14 16 18 20 22 24 :
Instructions until prcfctch
Figure 4-1:
Limited time for prefetch
4.1. Stream Buffers
What we really need to do is to start the prefetch
before a tag transition can take place. We can do this
a mechanism called a
streum buffer (Figure 4-2). A
stream buffer consists of a series of entries, each consist-
ing of a tag, an available bit. and a data line.
When a miss occurs, the stream buffer begins
prefetching successive lines starting at the miss target.
As each prefetch request is sent out, the tag for the ad-
dress is entered into the stream buffer, and the available
bit is set to false. When the prefetch data returns it is
placed in the entry with its tag and the available bit is set
to true. Note that lines after the line requested on the
miss are placed in the buffer and not in the cache. This
avoids polluting the cache with data that may never be
Subsequent accesses to the cache also compare their
address against the first item stored in the buffer. If a
reference misses in the cache but hits in the buffer the
cache can be reloaded in a single cycle from the stream
buffer. This is much faster than the off-chip miss
penalty. The stream buffers considered in this section
are simple FIFO queues, where only the head of the
queue has a tag comparator and elements removed from
the buffer must be removed strictly in sequence without
skipping any lines. In this simple model non-sequential
line misses will cause a stream buffer to be flushed and
restarted at the mtss address even if the requested line is
already present further down in the queue.
When a line is moved from a stream buffer to the
cache, the entries in the stream buffer can shift up by one
and a new successive address is fetched. The pipelined
interface to the second level allows the buffer to be filled
at the maximum bandwidth of the second level cache,
and many cache lines can be in the process of being
fetched simultaneously.
For example, assume the
latency to refill a 16B line on a instruction cache miss is
12 cycles. Consider a memory interface that is pipelined
and can accept a new line request every 4 cycles. A
four-entry stream buffer can provide 4B instructions at a
rate of one per cycle by havmg three requests outstand-
ing at all times. Thus during sequential instruction execu-
tion long latency cache misses will not occur. This is in
contrast to the performance of tagged prefetch on purely
sequential reference streams where only one line is being
prefetched at a time. In that case sequential instructions
will only be supplied at a bandwidth e
tion every three cycles (i.e., 12 cycle
ual to one instruc-
atency / 4 instntc-
tions per line).
From omceowr To ~roauot
4-2: Sequential stream buffer design
Figure 4-3 shows the performance of a four-entry
instruction stream buffer backing a 4KB instruction
cache and a data stream buffer backing a 4KB data
cache, each with 16B lines. The graph gives the cumula-
tive number of misses removed based on the number of
lines that the buffer is allowed to prefetch after the
original miss. (In practice the stream buffer would prob-
ably be allowed to fetch until the end of a vtrtual
memory page or a second-level cache line. The major
reason for
lotting stream buffer performance as a func-
tion of pre etch length is to get a better idea of how far
streams continue on average.)
Most instruction
references break the purely sequential access
the time the 6th successive line is fetched, w
attem by
‘le many
patterns end even sooner. The exceptions
to this appear to be instruction references for
data references for
linpuck liver
is probably an anomaly
since the 14 loops of the program are executed squen-
tially, and the first 14 loops
do not generally call other
procedures or do excessive branching, which would
cause the sequential miss pattern to break. The data
reference pattern of /inpack can be understood as fol-
lows. Remember that the stream buffer is only respon-
sible for providing
lines that the
cache misses on. The
inner loop of
(i.e., saxpy) performs an inner
roduct between one row and the other rows of a matrix.
e first use of the one row loads it into the cache. After
that subsequent misses in the cache (except for mapping
conflicts with the first row) consist of subsequent lines of
the matrix. Since the matrix is too large to fit in the
onchip cache, the whole matrix is passed through the
cache on each iteration. The stream buffer can do this at
the maximum bandwidth provided by the second-level
cache. Of course one prerequisite for this is that the
reference stream is unit-stride or at most skips to every
other or every third word. If an array is accessed in the
non-unit-stride direction (and the other dimensions have
non-trivial extents) then a stream buffer as presented
here will be of little benefit.
I Kay? - LlI-cache
- LIDach
“0 1 2 3 4 5 6 7 8 9 10 11 12
13 14 IS 16
4-3: Sequential stream buffer performance
4.2. Multi-Way Stream Buffers
Overall, the stream buffer presented in the previous
section could remove 72% of the instruction cache
misses, but it could only remove 25% of the data cache
misses. One reason for this is that data references tend to
consist of interleaved streams of data from different
sources. In order to improve the performance of stream
buffers for data references, a multi-way stream buffer
was simuiated (Figure 44). It consists of four stream
buffers in parallel. When a
miss occurs
in the data cache
that does not hit in any stream buffer, the stream buffer
hit least recently is cleared (i.e., LRU replacement) and it
is started fetching at the miss address.
Figure 4-5 shows the performance of the multi-way
stream buffer on our benchmark set. As expected, the
performance on the instruction stream
remains virtually
unchanged. This means that the simpler single stream
buffer wiIl suffice for instruction streams. The multi-
stream buffer does signticantl improve the
mance on the data side, however. d
P* verall, the mu n-way
stream buffer can
remove 43%
of the misses for the six
programs, almost twice the performance of the single
stream buffer. Although the matrix operations of liver
experience the greatest improvement (it changes from
7% to 60% reduction), ah of the programs benefit to
some extent.
To “al 1011~ each.
4-4: Four-way stream buffer design
- Ll D-x&
0 12 3 4 5 6 7 8 9 10111213141516
Length of Cway smeam Nn
4-5: Four-way stream buffer performance
43. Stream Buffer Performance vs. Cache Size
Figure 4-6 gives the erformance of single and 4-
stream buffers with 1
lines as a function of cache
size. The instruction stream buffers have remarkably
constant performance over a wide range of cache sizes.
The data stream buffer performance generally improves
as the cache size increases. This is especially true for the
single stream buffer, whose performance increases from
a 15% reduction in misses for a data cache size of 1KB
to a 35% reduction in misses for a data cache size of
128KB. This is probably because as the cache size in-
creases, it can contain data for reference patterns that
access several sets of data, or at least all but one of the
sets. What misses that remain are more likely to consist
of very long single sequential streams. For example, as
the cache size increases the percentage of compulsory
misses increase, and these are more likely to be sequen-
tial in nature than
conflict or capacity misses.
1GQr 1
rmgle scquauid stream buffer
90 OLIIssfhe
- ‘l-way sequenti stream buffer
Cl Ll D-each
“1 2 4
16 32 64 128
4-6: Stream buffer performance vs. cache size
4.4. Stream Buffer Performance vs. Line Size
Figure 4-7
gives the performance of single and 4-
way stream buffers as a function of the line size in the
stream buffer and 4KB cache. The reduction in misses
provided by a single data stream buffer falls by a factor
of 6.8 going from a line size of 8B to a line size of 128B,
while a Cway stream buffer’s contribution falls by a
factor of 4.5. This is not too surprising since data
references are often fairly widely distributed. In other
words if a piece of data is accessed, the odds that another
iece of data 128B away will be needed soon are fairly
ow. The single data stream buffer performance is es -
cially hard hit compared to the multi-way stream bu F er
because of the increase in conflict misses at large line
1 8o
[ 70
.I 60
i 5o
g 30
d: 20
- - single requcntid rueam buffer
- 4-way SqLwntial ItraM tuffu
0 Ll I-c&The
Cl Ll D-x&c
16 32 64 128 256
Cache Line Size. in Bytes
4-7: Stream buffer performance vs. line size
The instruction stream buffers perform well even out
to 128B line sizes. Both the 4-way and the single stream
buffer still remove at least 40% of the misses at 128B
line sizes, coming
from an 80% reduction with 8B
lines. This is probably due to the large granularity of
conflicting instruction reference streams,
the fact
that many procedures are more than 128B long.
5. Conclusions
Small miss caches (e.g., 2 to 5 entries) have been
shown to
effective in reducing data cache conflict
misses for direct-mapped caches in range of 1K to 8K
bytes. They effectively remove tight conflicts where
misses alternate between several addresses that map to
the same line in the cache. Miss caches are increasingly
beneficial as Iine
and the percentage
conflict misses increases. In general it appears that as
the percentage of conflict misses increases, the percent of
these misses removable
by a
miss cache also mcreases,
resulting in an even steeper slope for the performance
improvement possible by using miss caches.
Victim caches are an improvement to miss caching
that saves the victim of the cache miss instead of the
target in a small associative cache. Victim caches are
even more effective at removing conflict misses than
miss caches.
Stream buffers prefetch cache lines after a missed
cache line. They store the line until it is requested
cache miss (if ever) to avoid unnecessary pollution of
cache. They are particularly useful at reducing the num-
ber of capacity and compulsory misses. They can take
full advantage of the memory bandwidth available in
ipelined memory systems for sequential references, un-
ilce previously discussed prefetch techniques such as
tagged prefetch or prefetch on miss. Stream buffers can
also tolerate longer memory system latencies since they
prefetch data much in advance of other prefetch tech-
niques (even prefetch always). Stream buffers can also
compensate for instruction conflict misses, since these
tend to be relatively sequential in nature as well.
Multi-wa stream buffers are a set of stream buffers
that can
pre etch down several streams
Multi-way stream buffers are useful for data references
that contain interleaved accesses to several different
large data structures, such as in array operations.
However, since the prefetching is of sequential lines,
only unit stride or near unit stride (2 or 3) access patterns
The performance improvements due to victim
caches and due to stream buffers are relatively or-
thogonal for data references. Victim caches work well
where references alternate between two locations that
map to
the same line
cache. They do not
but only do a better job of
data fetched
available for use. Stream buffers, however, achieve per-
formance improvements by prefetching data. They do
not remove conflict misses unIess the conflicts are
widely spaced in time, and the cache miss reference
stream consists of many sequential accesses. These are
precisely the conflict misses not handled well by a victim
cache due to its relatively small capacity. Over the
set of
six benchmarks, on average only 2.5% of 4KB
mapped data cache misses that hit in a four-entry victim
cache also hit in a four-way stream buffer for ccom;
yucc, grr, and liver. In contrast,
due to its se-